RTL design in Verilog, verification against independent reference models, computer architecture,
GPU programming, and taking designs through synthesis and physical layout.
An int8 matrix-multiply accelerator built around a 4×4 output-stationary systolic array, the same architecture as Google's TPU. It's memory-mapped onto my pipelined RISC-V processor, and the CPU drives it with ordinary loads and stores.
I ran a quantized handwritten-digit classifier on it: every hardware layer output matched NumPy bit for bit. Then I took the design from RTL to a placed-and-routed SkyWater 130nm layout with OpenLane: 0 DRC and LVS errors, and 100 MHz timing met at the typical corner.
Verification compared about 3.1 million multiply-accumulates against a NumPy golden model, and all 8 deliberately planted bugs were caught.
CUDA C++ · Tensor Cores (WMMA) · cuBLAS · Nsight Compute · Python
The int8 matrix multiply at the heart of quantized neural networks, written seven ways on the GPU. Each version fixes the previous one's bottleneck: memory coalescing, shared-memory and register tiling, packed dp4a instructions, and finally tensor cores.
Every kernel is checked exactly against a CPU reference at every size, and benchmarked on an NVIDIA T4 with a roofline analysis. It pairs with my accelerator: tensor cores are systolic arrays inside the GPU, and both designs come down to keeping the multipliers fed.
Measured on an NVIDIA T4 at 2048³: each kernel fixes the bottleneck of the one above it. cuBLAS is NVIDIA's library, for reference.
Single-cycle and five-stage RV32I cores, built to compare how pipeline hazards affect performance. The pipelined core forwards ALU results, stalls on load-use dependencies, and flushes younger instructions on taken branches.
I wrote my own assembler and instruction-set simulator as a golden model. Every program's final registers, memory and instruction count must match it exactly, including thousands of randomly generated instructions.
Instructions overlap across clock cycles; the curve is a forwarded result.
A set of synthesizable building blocks: UART, SPI master, synchronous FIFO, button debouncer, and a traffic-light state machine. A UART echo top level connects the receiver, FIFO and transmitter into one serial datapath.
Six self-checking testbenches cover randomized FIFO traffic, UART framing errors, SPI edge timing, and safety properties checked every cycle. CI runs every simulation and Verilator lint on each push.
UART echo simulation: the receiver decodes 0x48, queues it in the FIFO, and the transmitter sends it back. View on GitHub
Firmware, real-time systems, sensors and signal processing: hardware that interacts with the physical world.
Vital Sign Monitoring with mmWave Radar
TI IWR6843ISK · 77 GHz FMCW radar · signal processing · Stanford, May–June 2026
A contactless heart-rate and respiration monitor. Instead of wearable or contact sensors like PPG, it measures sub-millimeter chest displacement from the phase of the radar signal.
I derived and implemented the full signal-processing pipeline (range-FFT, DC offset correction, phase extraction and unwrapping, and slow-time FFT) and designed the chirp parameters to reach under 0.1 Hz frequency resolution. That's enough to separate breathing (0.2–0.5 Hz) from heart rate (1–1.6 Hz). Across multiple trials it reliably detected respiratory rate (14–19 bpm) and heart rate (61–80 bpm) from 1 m away.
Butter Bot
STM32 · ESP32S3 camera · I2C · UART · PWM · 3D printing · in progress, Fall 2026
An autonomous mini forklift inspired by the Butter Robot from Rick and Morty. It uses a camera to find a stick of butter, slides its forks under a small pallet, lifts it, and delivers it to a red drop-off marker.
An STM32 Nucleo-L4R5ZI-P runs the robot as an interrupt-driven state machine. It receives butter and marker positions from a XIAO ESP32S3 Sense camera over UART, reads heading from an LSM303AGR magnetometer over I2C, and drives two DC gearmotors and an SG92R servo with timer PWM. The 25-part 3D-printed body includes a parallel-link forklift that lifts the forks 30 mm while keeping them level.
RTOS Task Scheduler
STM32 NUCLEO-F446RE · FreeRTOS · C
Multitasking firmware with concurrent tasks for sensor polling, motor control, status LEDs and a UART command shell, coordinated through task priorities, preemption, queue-based messaging and mutex-protected output.
Commands like motor open, led on and status can be issued live over serial. The hardware is an STM32 NUCLEO-F446RE, an SG90 servo, and an external 5 V supply.
A solar-powered USB charger prototype with a LiPo battery and a DC-DC boost converter.
Useless Box
A motorized box that flips its own switch off using a mechanical lever and a limit switch.
Machine learning from scratch, interactive learning tools, and web apps.
Mini LLM
Python · PyTorch
A character-level transformer. Its attention heads use a causal mask, so each position only attends to itself and earlier characters. The command-line interface trains on a text file and samples from a saved checkpoint.
Each character attends only to itself and earlier ones.
AstroML Journey
React · Vite
An app that teaches machine learning through six space-themed lessons. React state tracks quiz answers and completed missions, and the stage selector unlocks the next world after a correct answer.